AGSTU Sierra™
Next generation of OS kernels for demanding applications!

AGSTU Sierra™ is a Smart Ultra-Fast Hardware RTOS Accelerator for FPGA-based embedded systems

• No CPU overhead for clock-tick processing, task scheduling, queue management…
• Deadline control in Hardware and overload monitoring
• Direct task activation from external hardware signals — no IRQ/ISR path required.
• Simple FPGA integration with validation support through a regression testbench framework
• Built-in event logging with high-resolution timestamp support

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User Reference Manual · Standard Editions

Key features

Special AGSTU Sierra™ function:
No CPU overhead for clock-tick processing, task scheduling, queue management…

Hardware-accelerated RTOS services eliminate software kernel overhead, reduce latency, and maximize CPU time for application processing.

Special AGSTU Sierra™ function:
Deadline control in Hardware

AGSTU Sierra™ continuously monitors task deadlines in hardware without consuming CPU resources. Deadline violations can be detected immediately, enabling fast corrective actions, early overload detection, and improved system reliability

Special AGSTU Sierra™ function:
Direct Hardware Task Activation

AGSTU Sierra™ allows selected external hardware events to activate waiting tasks directly, bypassing the traditional IRQ/ISR path. This reduces interrupt-to-task latency, minimizes jitter, and removes CPU overhead from time-critical event handling.

Built-in event logging with high-resolution timestamp support

AGSTU Sierra™ includes built-in event logging support that records RTOS events with precise timestamps derived from either the system clock or RTOS clock-tick source. This enables detailed timing analysis, performance measurement, and verification of real-time behavior.

Regression Test Framework Included

Delivered with a dedicated regression and verification framework for automated testing of RTOS functionality and HW/SW integration of AGSTU Sierra™.

Proven in Real FPGA Projects

AGSTU Sierra™ has been used for many years in more than 100 FPGA student and research projects and has also been evaluated and sold to industrial companies.

Portable AGSTU Sierra™ IP Core

Delivered as a portable encrypted FPGA IP core with lightweight software drivers and a flexible integration interface.

Sierra™ IP is Ready-to-Use for Altera® Nios® II and Nios® V

Optimized for seamless integration with Altera FPGA embedded systems based on Nios® II and Nios® V processors.

New possibilities

Customer-specific advanced functions can be integrated into the AGSTU Sierra™ IP framework. Future enhancements and feature development are driven by customer needs.

What our customers say

Simple to use

The Sierra is easy to use and configure for users on all levels. It simplifies working with task based systems while still being powerful to get the job done.

Maya Isaksson

Suitable for small embedded systems

Fredrik Skarhed