Products

Standard Edition

• 8 Tasks
• 8 Priority Levels
• 4 Semaphores
• 4 Event Flags
• Periodic and Delay Timers
• Deadline Control
• External Task Interrupt Support
• Target devices Altera Nios II and NIOS V

The standard edition is validated and ready for integration.

Need More?

Sierra can be tailored with additional tasks, priorities, semaphores, flags, timers, and interrupt channels. The Sierra architecture is technology-independent and can also be adapted to other FPGA vendors and RISC-V processor platforms.

Contact AGSTU to discuss custom configurations and platform support.

• AGSTU Sierra™ for Nios® II
  Hardware RTOS accelerator for Altera® Nios® II FPGA embedded systems.

• AGSTU Sierra™ for Nios® II — Evaluation Version
  Free time-limited version for evaluation and integration testing.

• AGSTU Sierra™ for Nios® V
  Hardware RTOS accelerator for modern Altera® Nios® V FPGA embedded systems.

• AGSTU Sierra™ for Nios® V — Evaluation Version
  Free version for technical evaluation and FPGA integration testing.

Technical documentation, API references, and FPGA integration manuals for Sierra™ version 10.03.15.

Included with all Sierra™ products:

• Integrated logging support

• Regression testbench framework

• Lightweight software drivers

• FPGA integration support

• HW/SW integration examples