News

AGSTU announces availability of the Sierra™ Hardware RTOS Accelerator for Altera® Nios® V embedded systems. The new release extends Sierra™ support from Nios® II to the modern RISC-V based Nios® V processor family.

Sierra™ accelerates selected RTOS functions directly in hardware, enabling deterministic ultra-low latency real-time behavior with reduced CPU overhead and minimized interrupt load. The architecture removes the need for a traditional periodic RTOS kernel tick by handling timing-related functions in dedicated hardware.

The release also introduces:
• Integrated logging functionality
• Regression testbench support
• Lightweight software integration for FPGA-based embedded systems

Evaluation editions are available for selected Altera® FPGA platforms. Sierra’s technology-independent architecture also enables integration with other FPGA vendors and RISC-V processor platforms upon request.

For evaluation requests and licensing information, please contact:
sierra_evaluation@agstu.com